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D3.2 Report on the measurements of the E-Band digital base-band subsystems 1

Executive Summary

This report documents the next step in the design and implementation of the digital base-band. It represents an intermediate step between the simulation and the implementation of the DBB. On one side, the final architecture is analysed by completing the simulations performed in D3.1. On the other side, a first step towards the implementation of the DBB is performed, by specifying the internal interfaces of the subsystems. Therefore, this document consists of two parts.

From the results of D3.1, some issues must be further analysed to meet the requirements of D1.2, looking for solutions by changing the DBB architecture and/or employing more sophisticated DBB algorithms. Concretely, DC component and frequency-selective IQ imbalance are deeply analysed to reduce the performance degradation and meet the requirements.

Once the architecture of DBB is fixed and the requirements can be fulfilled, this document presents the system architecture of the DBB. This includes the definition of external and internal interfaces and the specification of the subsystems. The requirements of D1.2 are applied to the DBB subsystems that will directly influence the design and implementation of the modules. Therefore, this document focuses on the design of the DBB, especially in defining the internal interfaces of the subsystems in order to allow the beginning of the implementation.

Finally, a first insight in the hardware architecture of the transceiver is provided. Hardware components are identified to implement the DBB and the interconnection with other transceiver modules is analysed.




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  • Project acronym

  • Project title
    Energy Efficient E-band transceiver for backhaul of the future networks

  • Project reference

  • Project coordinator
    CEIT (Spain)

  • Start date: 01/12/2012
    End date: 31/05/2016

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